1. Field of the Invention
The present invention relates to a receiving apparatus that can be connected to a transmitting apparatus through a plurality of transmission lines and its receiving method.
2. Description of the Related Art
A conventional inter-chip transmission system will be described below.
FIG. 17 is a block diagram showing an example of a configuration of bidirectional transmission in a conventional inter-chip transmission system, which shows an example of a state of a physical layer in high-speed signal transmission between a chip A (CHIP_A) and chip B (CHIP_B). Each chip has four transmitting circuits (TX0, TX1, TX2, TX3) and four receiving circuits (RX0, RX1, RX2, RX3). In this system, one transmitting circuit and one receiving circuit constitute a pair, and a pair of a transmission line from one transmitting circuit of the chip A to one receiving circuit of the chip B and transmission line from one transmitting circuit of the chip B to one receiving circuit of the chip A is referred to as “lane”. Connections of all lanes between the chip A and chip B are referred collectively as “link”. That is, the maximum link width between the chip A and chip B is four lanes. Such an inter-chip transmission system is standardized as, e.g., PCI Express.
At power-on time or hard rest time, each chip determines bit synchronization, symbol synchronization, deskew between lanes, link width, lane order, link data rate, before activation of the link. The link width is set to a largest possible value, and data rate is set to a highest possible value. At the activation time, optimization of a transmission waveform or optimization of a reception waveform according to a state of the transmission system is not performed.
Data check is performed in a data link layer and, when a plurality (e.g., three times) of consecutive reception errors take place, it is determined that link abnormality has occurred, and link down is made. A coding method and an error correction method are fixed irrespective of transmission quality of the transmission system.
The above link can assume four states: 0, 0s, 1, and 2. The state 0 is a normal operating state. The state 0s is a state where transmission operation is stopped but CDR and CLK operate. The state 1 is a state where transmission operation is stopped and CDR and CLK are also stopped. The state 2 is a state where transmission operation is stopped and CDR, CLK, and main power supply are stopped.
The states 0s, 1, and 2 are compared with one another. The state 0s has a smaller effect of power reduction and a shorter wake-up time. The state 1 has a moderate effect of power reduction and a moderate wake-up time. The state 2 has a larger effect of power reduction and a longer wake-up time.
An inter-chip transmission system including a transmitting chip and a receiving chip will next be described.
FIG. 18 is a block diagram showing an example of a configuration of one-way transmission in a conventional inter-chip transmission system. The inter-chip transmission system of FIG. 18 includes a transmitting chip 1 and a receiving chip 2. The transmitting chip 1 includes n+1 transmitting circuits 11 (TX0, TX1, . . . , Txn). The receiving chip 2 includes n+1 receiving circuits 21 (RX0, RX1, . . . , RXn) and a logic circuit 22 in a higher layer.
All the transmitting circuits 11 operate according to an externally supplied common basic clock.
FIG. 19 is a block diagram showing an example of a configuration of a conventional transmitting circuit. The transmitting circuit of FIG. 19 includes an encode circuit 111, an FFE (Feed-Forward Equalization) 112, and an amplifier 113.
When parallel transmission data synchronized with a clock is input to the transmitting circuit, the encode circuit 111 performs 8B/10B coding for the transmission data to shorten the length of consecutive identical digits, embeds a basic clock component in the resultant data, and performs parallel-to-serial conversion, to thereby output a serial signal. The FFE 112 pre-emphasizes a harmonic component of the serial signal. The amplifier 113 in the last stage of the transmitting circuit amplifies the amplitude of the supplied signal to a required amplitude and makes impedance matching between the resultant signal and transmission line to thereby drive the transmission path. The FFE 112 in this example is a three-tap FFE, and the tap coefficients K0 to K2 are set in accordance with the emphasis amount. The gain K3 of the amplifier 113 is set so that the output amplitude has a predetermined value.
FIG. 20 is a block diagram showing an example of a configuration of a conventional receiving circuit. The receiving circuit of FIG. 20 includes a CDR (Clock Data Recovery) 121 and a DECISION circuit 122.
The CDR 121 is constituted by a PLL (Phase Locked Loop) circuit. The PLL circuit is constituted by a phase comparison circuit, a charge pump, a low-pass filter, a VCO, and an M/N division circuit. The PLL circuit compares timing information (edge) of input data and timing information (edge) of VCO (Voltage Controlled Oscillator) output to thereby generate a clock synchronized with input data.
The DECISION circuit 122 determines input data (DATA-IN) transmitted from the transmitting circuit 11 at the timing of a clock output from the CDR 121.
What is required for the PLL circuit is to take in, without fail, the input data with a reasonable take-in time, to keep a locked state with every input data pattern, to have excellent output jitter characteristics, to prevent jitter from increasing in every input data pattern, and to keep a locked state even with data containing consecutive identical digits while preventing output clock jitter from increasing. In high-speed transmission in which the transmission rate exceeds gigabits per second (Gbps), level of the requirements gets higher, so that it is impossible to satisfy the requirements with the abovementioned fundamental configuration.
In order to cope with the above problem, there is proposed a PLL circuit modified such that the output clock jitter of the PLL circuit is not increased even when the transition rate of the input data is low (refer to, e.g., Patent Document 1: Jpn. Pat. Appln. Laid-Open Publication No. 2004-88476). The PLL circuit of Patent Document 1 is about twice the scale of a PLL circuit having a basic configuration.
Further, there is proposed a PLL circuit modified in order to satisfy jitter transfer and jitter tolerance characteristics of the PLL circuit at a specified operating temperature and within a range of power supply voltage (refer to, e.g., Patent Document 2: Jpn. Pat. Appln. Laid-Open Publication No. 2002-359555). A potential generation circuit used in the PLL circuit of Patent Document 2 is created based on a BGR (Band Gap Reference) circuit, so that the scale of this PLL circuit becomes larger than that of a PLL circuit having a basic configuration.
In order to widen the capture range and lock range of the PLL, it is only necessary to widen the PLL loop bandwidth. However, in order to achieve stable operation with a longer consecutive identical digit pattern, the PLL loop needs to be narrowed. In order to realize the opposite requirements, there is proposed a PLL circuit having a loop that locks onto a reference clock and a loop that locks onto input data (refer to, e.g., Patent Document 3: Jpn. Pat. Appln. Laid-Open Publication No. 2005-210540). The PLL circuit of Patent Document 3 requires the reference clock, and the scale thereof becomes larger than that of a PLL circuit having a basic configuration.
As described above, when the performance of the PLL circuit is increased in order to speed up transmission speed, the scale of the circuit is increased, resulting in an increase in power consumption and cost.